Method of manufacturing semiconductor device and semiconductor integrated circuit device

ABSTRACT

A method of manufacturing a semiconductor device comprises providing on a semiconductor substrate a mask pattern having a fully opened region and a partially opened region. Impurities are selectively introduced into an impurity introduction region of the semiconductor substrate through the fully opened region and the partially opened region of the mask pattern to form areas having high and low impurity densities in the impurity introduction region.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to the configurations of the source and drain regions of a MOS transistor forming a part of a semiconductor integrated circuit device and, more particularly, to a method of manufacturing for determining the impurity density at boundaries between the channel region and the source and drain regions.

[0002] In order to prevent the deterioration of the characteristics of MOS transistors having a small channel length due to hot carriers which has arisen as MOS transistors have become finer, it has become common to employ an LDD structure having low-density diffusion layer regions in the vicinity of the edges of the gate electrode, i.e., in the vicinity of the boundaries between the channel region and the source and drain regions to relax a high electric field in the vicinity of the drain edge.

[0003]FIG. 7 is a schematic sectional view illustrating a process of forming source and drain diffusion layer regions of a conventional LDD type MOS transistor.

[0004] Impurities are introduced using first impurity ion beams 702 to form low-density diffusion layers of a second conductivity type in regions on a semiconductor substrate of a first conductivity type which have been selected using a patterned resist 701.

[0005] At this time, since a thick silicon oxide film 707 and a gate electrode 705 made of polysilicon or the like serve as a mask to select the regions into which impurities are to be introduced just like the resist 701, the impurities are introduced only to regions under a thin silicon oxide film 708 which are not covered by the gate electrode and the resist (FIG. 7A).

[0006] Next, after forming a silicon oxide film layer 704 on the entire surface by means of deposition using CVD or the like (FIG. 7B), anisotropic etching is performed on the silicon oxide film layer 704 to form side walls 706 constituted by silicon oxide films on the gate electrode 705 (FIG. 7C).

[0007] Thereafter, impurities are introduced again but, this time, using second impurity ion beams 709 to form high-density diffusion layers of the second conductivity type in regions selected using a patterned resist 711 and, further, thermal diffusion is performed.

[0008] Then, the regions directly under the silicon oxide film side walls 706 become low-density diffusion layers and the rest of the source and drain regions become high-density diffusion layers (FIG. 7D).

[0009] When a conventional MOS transistor having an LDD structure is formed, as shown in FIG. 6, a pattern 602 as an impurity introduction mask for selecting regions into which impurities for forming low-density impurity layers and high-density impurity layers are introduced, is drawn to cover the entire surface of a source region 603, a drain region 604, and a channel region directly under a gate electrode 601 which generally serve as an active region.

[0010] It is widely known that such an LDD structure allows a MOS transistor to have higher resistance to hot carriers.

[0011] However, the cost of a conventional LDD type MOS transistor could be increased by complicated processes involved such as the two impurity introduction processes and the process of forming the silicon oxide film side walls as described above.

[0012] Further, although an LDD type MOS transistor has excellent resistance to hot carriers, it is vulnerable to surge stresses such as external static electricity, and a conventional (non-LDD) type transistor whose source and drain regions are constituted only by high-density diffusion layers is better with respect to resistance to breakage due to static electricity. As a result, semiconductor integrated circuit devices have been sometimes manufactured by adding a process for fabricating conventional (non-LDD) type MOS transistors having a relatively large channel length to be used as an input protection circuit and an output transistor instead of those having the LDD structure.

SUMMARY OF THE INVENTION

[0013] In order to solve the above-described problems, the present invention employs the following means.

[0014] As a first means, when the high-density diffusion layers in the source and drain regions of a MOS transistor are formed, a resist or the like for selecting the regions into which impurities are to be introduced is partially left in the vicinity of the side walls of the gate electrode, and thermal diffusion is performed after partially introducing impurities for forming the high-density diffusion layers to form pseudo low-density diffusion layers.

[0015] As a second means, MOS transistors formed using the first means are used only for an inner circuit which is not directly subjected to surge stresses such as external static electricity, and an input protection circuit and an output transistor are constituted by MOS transistors whose source and drain regions are formed by high-density diffusion layers obtained by not leaving the resist in the vicinity of the side walls of the gate electrode.

[0016] The first means allows low-density diffusion layers to be formed simultaneously in one process of introducing impurities for forming high-density diffusion layers.

[0017] This makes it possible to provide an LDD type MOS transistor with less process steps at a low cost.

[0018] The second means makes it possible to form both of an LDD type MOS transistor and a conventional (non-LDD) type MOS transistor in one process of introducing impurities for forming high-density impurity regions. It is therefore possible to provide a reliable semiconductor integrated circuit device at a lower cost.

BRIEF DESCRIPTION OF THE DRAWING

[0019]FIG. 1 is a schematic plan view of an LDD type MOS transistor according to a first embodiment of the present invention;

[0020] FIGS. 2A, 2A′, 2B and 2B′ are schematic sectional views illustrating a part of a process of manufacturing the LDD type MOS transistor according to the first embodiment of the present invention;

[0021]FIG. 3 is a schematic plan view of an LDD type MOS transistor according to a second embodiment of the present invention;

[0022]FIG. 4 is a schematic plan view of an LDD type MOS transistor according to a third embodiment of the present invention;

[0023]FIG. 5 is a simplified block diagram of a semiconductor integrated circuit device according to a fourth embodiment of the present invention;

[0024]FIG. 6 is a schematic plan view of an LDD type MOS transistor according to the prior art; and

[0025]FIGS. 7A to 7D are schematic sectional views illustrating a part of a process of manufacturing the LDD type MOS transistor according to the prior art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Embodiments of the present invention will now be described with reference to the drawings.

[0027]FIG. 1 is a schematic plan view illustrating an LDD type MOS transistor according to a first embodiment employing the first means according to the present invention.

[0028]FIGS. 2A to 2B′ are schematic sectional views illustrating a process of forming the source and drain regions of the LDD type MOS transistor according to the first embodiment of the present invention. The section A-A′ in FIG. 1 corresponds to FIG. 2A′, and the direction perpendicular to A-A′ in FIG. 1 corresponds to FIG. 2A.

[0029] In FIG. 1, since a mask pattern 102 for introducing impurities meanders around the edges of a gate electrode 101, impurities introduced using impurity ion beams 202 at the processes shown in FIG. 2A and FIG. 2A′ are introduced only in the hatched areas in FIG. 1.

[0030] As a result, some areas are left in the vicinity of the edges of the gate electrode where impurities are not introduced.

[0031]FIG. 2B and FIG. 2B′ are sectional views schematically illustrating the distribution of impurities after thermal diffusion is performed in the states shown in FIG. 2A and FIG. 2A′. As shown in FIG. 2B and FIG. 2B′, source and drain diffusion regions are formed by thermally diffusing the introduced impurities. However, if the areas where the impurities have not been introduce are sufficiently small, impurities in areas 204 where the impurities have been partially introduced are thermally diffused. As a result, the areas 204 where the impurities have been partially introduced become low-density diffusion layers 207, and areas 203 where the impurities have been continuously introduced become high-density diffusion layers 206.

[0032]FIG. 3 is a plan view illustrating a second embodiment utilizing the first means according to the present invention.

[0033] In FIG. 3, the pattern 102 of a mask for introducing impurities is illustrated in the form of narrow stripes in the vicinity of the edges of a gate electrode.

[0034] Therefore, as in FIG. 1 and FIGS. 2A to 2B′, low-density diffusion layers are formed in the vicinity of the edges of the gate electrode, and the remaining regions where the impurities have been continuously and widely diffused become a high-density diffusion layers.

[0035]FIG. 4 is a plan view illustrating a third embodiment utilizing the first means according to the present invention. in FIG. 4, the pattern 102 of a mask for introducing impurities is illustrated in the form of small dots in the vicinity of the edges of a gate electrode.

[0036] Therefore, again as in FIG. 1 and FIGS. 2A to 2B′ low-density diffusion layers are formed in the vicinity of the edges of the gate electrode, and the remaining regions where the impurities have been continuously and widely diffused become high-density diffusion layers.

[0037] In the above description, in order to make the distribution of the impurities in the low-density diffusion layers more uniform, the preferred pattern pitch is preferably 1 μm or less for the portion A-A′ in FIG. 1 where the pattern of the mask pattern 102 for introducing impurities meanders and for the portions in FIG. 4 where the mask pattern for introducing impurities, i.e., the pattern 102 in the form of small dots, are present and not present.

[0038]FIG. 5 is a simplified block diagram of a semiconductor integrated circuit device which is a fourth embodiment utilizing the second means according to the present invention.

[0039] Since LDD type MOS transistors and conventional (non-LDD) type MOS type transistors can be freely formed in the same semiconductor integrated circuit device on the same process step by leaving or not leaving a resist which is patterned by a mask pattern for introducing impurities in the vicinity of the edges of the gate electrode, as shown in FIG. 5, only an input protection circuit an output transistor which are directly subjected to surge stresses such as external static electricity are constituted by conventional (non-LDD) type MOS transistors having a relatively large channel length, and the rest of the circuit is constituted by high-speed LDD type MOS transistors having excellent resistance to hot carriers and a shorter channel length.

[0040] As described above, according to the present invention, when the high-density diffusion layers in the source and drain regions of a MOS transistor are formed, a resist or the like for selecting the regions into which impurities are to be introduced is partially left in the vicinity of the side walls of the gate electrode, and thermal diffusion is performed after partially introducing impurities for forming the high-density diffusion layers to form pseudo low-density diffusion layers. This results in an advantage in that it is possible to provide LDD type MOS transistors with less process steps at a low cost.

[0041] Further, according to the method of manufacturing a semiconductor device of the invention, it is possible to simultaneously form LDD type MOS transistors and conventional (non-LDD) type MOS transistors in the same semiconductor integrated circuit. As a result, there is an advantage in that a reliable semiconductor integrated circuit device can be provided at a lower cost by using LDD type MOS transistors for an inner circuit which is not directly subjected to surge stresses such as external static electricity and by configuring an input protection circuit and an output transistor using conventional (non-LDD) type MOS transistors whose source and drain regions are constituted only by high-density diffusion regions. 

What is claimed is:
 1. A method of manufacturing a semiconductor device wherein a mask pattern is provided on a semiconductor substrate to introduce impurities selectively and an impurity introduction region is formed in the vicinity of the surface of said semiconductor substrate by introducing impurities into said semiconductor substrate through said mask pattern, wherein areas having different impurity densities are formed in said impurity introduction region depending on the shape of said mask pattern.
 2. The method of manufacturing a semiconductor device according to claim 1, wherein that said introduction of impurities is carried out by implanting impurity ions in said semiconductor substrate using ion beams and by forming said impurity introduction region by means of thermal diffusion.
 3. The method of manufacturing a semiconductor device according to claim 1, wherein that said semiconductor substrate is of a first conductivity type and said impurities are of a second conductivity type.
 4. The method of manufacturing a semiconductor device according to claims 1, wherein that said impurity introduction region constitutes a source diffusion layer region and a drain diffusion layer region of a MOS type transistor and wherein that said source diffusion layer region and drain diffusion layer region have a structure that a high-density impurity diffusion layer and a low-density impurity diffusion layer are adjacent to each other.
 5. A semiconductor integrated circuit device comprising MOS type transistors including a source diffusion layer region and a drain in diffusion layer region, wherein the source diffusion layer regions and the drain diffusion layer regions of a part of the MOS type transistors have a structure wherein a high-density impurity diffusion layer and a low-density impurity diffusion layer are adjacent to each other, and wherein the source diffusion layer regions and the drain diffusion layer regions of the other part of the MOS type transistors have a structure constituted by a high-density impurity diffusion layer.
 6. The semiconductor integrated circuit device according to claim 5, further comprising an external circuit inputting signals from outside or outputting signals to outside, and an internal circuit connected to the external circuit, wherein the internal circuit includes the part of the MOS type transistor and the external circuit includes the other part of the MOS type transistor. 